Chapter 4

 

Bipolar Junction Transistors (BJTs)

 

 

 

In the previous chapter we outlined how the semiconductor diode is described to Spice using a diode element and model statement.  Further, we illustrated how the terminal characteristics of a diode are modeled within Spice and how the user can alter the parameters of this model to more closely characterize specific diode behavior.  In this chapter on the bipolar junction transistor (BJT) we shall proceed in a similar fashion, first outlining the two statements that are required to describe a BJT to Spice.  This will then be followed by a brief description of the model used to represent the BJT within Spice.  On completion of this, we shall use Spice to investigate the low-frequency behavior of various types of electronic circuits containing BJTs.  The types of circuits that will be simulated will range from single npn and pnp transistor amplifiers to multiple-transistor amplifier circuits, as well as circuits that utilize the transistor as an on-off switch.

 

4.1 Describing BJTs To Spice

 

Two statements are required to describe any particular semiconductor device to Spice. One statement is necessary to describe the nature of the semiconductor device and the manner in which it is connected to the rest of the network, and the other statement is required to describe the parameters of the built-in model of the semiconductor device described by the first statement.  In the following we shall describe these two statements as they apply to the BJT.

 

 

Fig. 4.1: Spice element description for the npn and pnp BJT. Also listed is the general form of the associated BJT model statement. A partial listing of the parameter values applicable to either the npn or pnp BJT given in Table 4.1.

 

 

4.1.1 BJT Element Description

 

The presence of a BJT in a circuit is described to Spice through the Spice input file using an element statement beginning with the letter Q.  If more than one transistor exists in a circuit, then a unique name must be attached to Q to uniquely identify each transistor.  This is then followed by a list of the three nodes to which the collector, base, and emitter of the BJT are connected to.  One can also include the node that the substrate is connected to if it is an integrated transistor.  Subsequently, on the same line, the name of the model that will be used to characterize this particular BJT is given.  The name of this model must correspond to the name given on a model statement containing the parameter values that characterize this transistor to Spice.  Lastly, one has the option of specifying the number of BJTs that are considered to be connected in parallel.

 

For quick reference we depict the syntax for the Spice statement describing the BJT in Fig.  4.1.  Also shown is the syntax for the model statement (.MODEL) that must be present in any Spice input file that makes reference to the built-in BJT model of Spice.  This statement defines the terminal characteristics of the BJT by specifying the values of particular parameters of the BJT model.  We shall discuss the model statement more fully next.

 

 

Fig. 4.2: The Spice large-signal BJT model for DC analysis.

 

 

4.1.2 BJT Model Description

 

As is evident from Fig.  4.1, the model statement for either the npn or pnp transistor begins with the keyword .MODEL and is followed by the name of the model used by a BJT element statement, the nature of the BJT (i.e.,  npn or pnp), and a list of the parameters characterizing the terminal behavior of the BJT, enclosed between brackets. The number of parameters associated with the Spice model of the BJT is rather large (40 in total), and their individual meanings are rather involved. Instead of trying to describe the meaning of each parameter of the BJT model, we shall simply outline the parameters of the Spice BJT model that are relevant to the discussion contained within this chapter.

 

The Spice BJT model is illustrated schematically in Fig.  4.2. The ohmic resistances of the base, collector, and emitter regions of the BJT are lumped into three linear resistances r_B, r_C and r_E, respectively.  The DC characteristics of the intrinsic BJT are determined by the nonlinear dependent current sources i_B and i_C.  The exact functional descriptions of these two currents - as adopted by Spice - are rather complex and will not be given here.  Interested readers can consult [Nagel, 1975] for more details.  For a transistor operated in its active mode, a first-order representation of these two currents can be described by the following two equations

(4.1)

and

(4.2)

 

Here I_S is the saturation current (similar to the diode saturation current) and V_T is the thermal voltage.  The constant B_F is the forward common-emitter current gain.  In Sedra and Smith, this constant is designated simply as B.  Spice attaches the subscript F to distinguish B_F from another current gain B_R which represents the common-emitter current gain of the same transistor when operated in the reverse mode (that is, with the emitter and collector interchanged). Finally, V_AF is the forward early voltage (denoted V_A in Sedra and Smith).

 

 

Table 4.1: A partial listing of the Spice parameters for a static BJT model.

 

 

A partial listing of the parameters associated with the Spice BJT model under static conditions is given in Table 4.1.  Also listed are the associated default values; if the value of a particular parameter is not specified on the .MODEL statement, the parameter assumes its default value. To specify a parameter value one simply writes, for example, Is=1e-14, Bf=100, etc..

 

4.1.3 Verifying NPN Transistor Circuit Operation

 

As the first example of this chapter, consider verifying the npn transistor circuit designed in Example 4.1 of Sedra and Smith and repeated here in Fig.  4.3.  This particular transistor circuit was designed to have a collector current of 2 mA and a collector voltage of +5 V.

 

For the purpose of design, the npn transistor was assumed to have a B_F = 100 and to exhibit a v_BE of 0.7 V at i_C = 1 mA.  The first condition can be directly specified on the BJT model statement using B_F=100, however, the latter condition needs to be translated into a BJT parameter.  From Eqn.  (4.2) we can write

(4.3)

 

Now, to make matters simpler, we shall assume that V_AF = infinity, thus reducing the above equation to

(4.4)

 

We can then solve to obtain I_S=1.8104 x 10^-15 A.  Our model statement for this particular transistor is then described to Spice using the following statement:

 

.model npn_transistor npn (Is=1.8104e-15 Bf=100) .

 

Notice that we did not specify the value of V_AF in the list of parameters, rather, we are relying on the default value assigned to V_AF.  Of course, the same could have also been done for the parameter B_F.

 

 

Assuming the nodes of the circuit are labeled as shown in Fig.  4.3, the corresponding Spice input file is listed in Fig.  4.4.  An operating point analysis command (.OP) is included in this file to tell Spice to calculate the DC operating point of this circuit.  Submitting this file to Spice, results in the following DC operating point information:

 

 

As is evident, the collector of the transistor (node 2) is at 4.9990 V and the collector current I_C, as inferred from the current supplied by the voltage source V_CC is 2.000 mA.  (The negative sign is a result of the convention used by Spice). Although, the collector voltage is not exactly at +5 V, the deviation from this value is extremely small (1 mV).  If one were to back-track to find why this error occurred, one would find that the value of V_T=25 mV assumed during the design phase is different than the value of V_T=25.89 mV that Spice used, assuming a circuit temperature of 27°C.  Repeating the design procedure outlined in Example 4.1 with the exact value of V_T=25.89 mV would result in an emitter resistance of R_E=7.0703 k-ohm and a collector voltage much closer to +5 V.

4.2 Using Spice as a Curve Tracer

 

A typical curve-tracer arrangement for measuring the i_C - v_CE characteristics of a transistor is illustrated in Fig.  4.5.  Here two independent sources v_CE and i_B are varied, and the collector current of the transistor is calculated.  The collector current would then be plotted as a function of v_CE and i_B.  For example, consider plotting the forward i_C - v_CE characteristics of a npn transistor characterized by I_S=1.8104 x 10^-15 A, B_F=100, and a forward Early voltage V_AF=35 V, for a base current of 10 uA.  Using the circuit displayed in Fig. 4.5 as a guide, we can create the Spice input file shown in Fig. 4.6 to accomplish this task.  We make use of the DC Sweep command available in Spice to vary the collector-emitter voltage of transistor Q₁ from 0 V to +10 V in 100 mV steps.  The resulting i_C - v_CE characteristic as calculated by Spice is displayed in Fig.  4.7.

 

 

 

 

Typically, one also wants to vary the base current i_B while at the same time varying v_CE of the transistor.  This can be accomplished with Spice by augmenting the DC Sweep command with another source name and the range of values it should be stepped through.  For example, the DC Sweep command required to sweep v_CE from 0 V to +10 V in 100 mV steps while at the same time sweeping i_B from 1 uA to 10 uA in 1 uA steps is simply the following:

 

.DC Vce 0V +10V 100mV Ib 1u 10u 1u.

 

In essence, this command tells Spice to perform the voltage sweep for each value specified by the current sweep.  (For those familiar with computer programming, this command should remind them of a set of programming loops: the inner sweep being nested within the outer sweep.)

 

Revising the Spice input deck with this augmented DC Sweep command and re-submitting this job to Spice, the i_C - v_CE characteristics displayed in Fig.  4.8 are obtained.  Clearly, other arrangements of the two independent sources are possible, thus allowing one to investigate other characteristics of the transistor. We encourage the reader to investigate some of them using the approach just outlined.

 

 

 

4.3 Spice Analysis of Transistor Circuits At DC

 

We are now ready to investigate the DC operating point of several simple transistor circuits using Spice.  Throughout this section we shall assume that the transistor is characterized by a B_F=100, exhibits a v_BE of 0.7 V at i_C=1 mA, and that its Early voltage is infinite.  The primary goal of this section is to determine, with the aid of Spice, the mode of operation that a transistor is working in.

 

Table 4.2: BJT modes of operation.

 

 

4.3.1 Transistor Modes of Operation

 

Depending on the bias condition imposed across the emitter-base junction (EBJ) and the collector-base junction (CBJ), different modes of operation of the BJT are obtained, as shown in Table 4.2. In the following we shall look at several transistor circuits and use Spice to determine the mode of operation of each.

 

 

Active Region

 

Consider the circuit shown in Fig.  4.9.  This same circuit was analyzed by Sedra and Smith using hand analysis in Example 4.2 of their text and transistor Q₁ was shown to be operating in the active region. We shall repeat this example using Spice to calculate the DC operating point and show that, indeed, transistor Q₁ is operating in the active mode.

 

 

 

A Spice description of this circuit is listed in Fig. 4.10 and a DC operating point analysis request is included. The results of the analysis are listed below:

 

 

Included amongst the list of node voltages is a partial summary of the DC operating point conditions associated with the transistor.  This includes the currents I_B and I_C, and the voltages V_BE, V_BC, and V_CE.  Other information is included in this list of operating point information but is not shown here.  Also, we do not show the small-signal parameters associated with the hybrid-pi model of the transistor, deferring discussion of this topic to a later stage.

 

What one should notice here, amongst this operating point information, is that the base-emitter junction is forward biased with V_BE=0.699 V and the collector-base junction is reversed biased with V_BC=-1.35 V; thus confirming that transistor Q₁ is indeed operating in its active region. One could have deduced this same information from the DC node voltages, but for multiple transistor circuits this can be a tedious endeavor.  Also, the collector and base currents agree reasonably well with the values calculated by hand analysis.

 

 

Saturation Region

 

If we increase the base voltage of the circuit of Fig. 4.11 from +4 V to +6 V, transistor Q₁ leaves the active region and moves into the saturation region. To see this, change the value of Vbb in the Spice input file shown in Fig. 4.10 to +6 V and re-run the Spice job. The results are:

 

 

As is evident, both V_BE and V_BC are forward biased, suggesting that Q₁ is operating in its saturation region. The saturation region of operation will be studied further in Sections 4.4 and 4.5.

 

Cutoff Region

 

Finally, if we reduce the base voltage to zero volts, then the transistor becomes cutoff.  Altering the Spice input deck to reflect this (i.e.,  setting Vbb=0) and re-running the Spice job results in the

following:

 

Here, both V_BE and V_BC are reversed biased, indicating that Q₁ is now cutoff.  Notice, however, that even under cutoff conditions the transistor is still conducting a base and collector current (and, of course, an emitter current).  These currents are mainly leakage currents associated with the two reverse biased junctions of the transistor.

 

 

 

 

4.3.3 Computing DC Bias of a PNP Transistor Circuit

 

The above circuit examples consisted of npn transistors only. In this next example we shall calculate the DC operating point of a circuit containing a pnp transistor.  As far as Spice is concerned, pnp transistor circuits are no more complicated than npn transistor circuits.

 

Consider the circuit shown in Fig.  4.11.  This example corresponds to Example 4.5 of Sedra and Smith, 3^rd Edition.  The Spice input file for this circuit is listed in Fig.  4.12 and the results of the DC analysis are shown below:

 

 

From the above results, it is obvious that the transistor is operating in the active mode.  Notice that the polarity of the transistor currents is opposite to those of a npn transistor operating in its active region (see the previous subsection). Further, one should also note that Spice defines a positive collector current of a pnp transistor as the current flowing into the collector. This is opposite to that which Sedra and Smith uses. One should be careful of this. When one compares the above Spice results with those generated by a simple hand calculation, say, for example, as was performed in Example 4.5 of Sedra and Smith, we find we are in very good agreement; about a 0.4% difference.

 

In the above analysis, the Early effect was neglected. In practise this is never the case. In the following, let us repeat the above analysis assuming the pnp transistor has an Early voltage V_AF of 100 V.  We shall then compare the resulting transistor collector current with that obtained previously when the Early effect was ignored.

 

Consider replacing the transistor model statement for the pnp transistor given in the Spice deck of Fig. 4.12 with the following one:

 

.model pnp_transistor pnp (Is=1.8104e-15 Bf=100 Vaf=100V).

 

Re-running the Spice job, we find in the Spice output file the following results: 

 

We see from the above results that the collector current is now 4.59 mA. This is in contrast to the previous situation when the Early effect was ignored, and a Spice analysis revealed a collector current of 4.58 mA. In the latter case, a similar result would also be obtained by a simple hand calculation, as was noted above. Thus, if we compare the result obtained by Spice with the Early effect included to that obtained by a simple hand calculation, we see a difference of about 0.2%.  For most practical engineering situations, a 5% to 10% accuracy obtained from a simple hand analysis is usually quite acceptable. But, more importantly, to account for the Early effect during hand analysis would complicate the analysis significantly that it would probably mask any insight.  Thus, if greater accuracy is thought necessary then one should make use of a detailed Spice analysis with the transistor Early effect included.

 

 

 

 

4.3.4 DC Operating Point of a Multiple Transistor Circuit

 

Consider the multiple transistor circuit shown in Fig.  4.13.  This same circuit was analyzed by hand for its node voltages and branch currents by Sedra and Smith, 3^rd Edition, and designated as Example 4.8 in their text.  We shall compute the DC operating point of this circuit using Spice.  The Spice input file is listed in Fig.  4.14 with an operating point analysis command included.  The results generated by Spice are listed below:

 

Comparing these results with those calculated by hand in Sedra and Smith, we see that the results generated by hand analysis (e.g., I_C1= 1.28 mA and I_C2= 2.75 mA) are quite close to the values generated by Spice.  Moreover, we see that both transistors are operating in the active mode.

 

In the following we repeat the analysis with each transistor having an Early voltage of 100 V. This requires that we modify the two-transistor model statement given in the Spice deck of Fig. 4.14 to the following:

 

.model npn_transistor npn (Is=1.8104e-15 Bf=100 Vaf=100V)

.model pnp_transistor pnp (Is=1.8104e-15 Bf=100 Vaf=100V)

 

On doing so, and re-submitting the revised Spice deck for processing, we obtain the following results:

 

Here we see that the collector current of Q₁ remains at 1.28 mA, but the collector current of Q₂ has increased to a level of 2.75 mA, a 0.02 mA increase. This example, like the previous one, demonstrates the effect that transistor Early voltage has on the DC bias levels in a circuit and shows that it is usually small. Thus, not accounting for it during a hand analysis seems reasonable.

 

 

 

Fig. 4.15: The small-signal BJT Spice model under static conditions.

 

4.4 BJT Transistor Amplifiers

 

Transistors operated in their active region find important applications as linear amplifiers.  Design and analysis of linear amplifiers is facilitated by the use of small-signal models for the BJT.  In the following we discuss the small-signal model used by Spice.

 

4.4.1 BJT Small-Signal Model

 

Under static and small-signal conditions, the linearized BJT Spice model is the familiar hybrid-pi model shown in Fig.  4.15.  Both the npn and pnp transistor have the same hybrid-pi model, so we make no distinction between the two.  The transconductance g_m is related to the DC bias current I_C according to the following

(4.5)

 

Similarly, the input and output resistances are also related to the transistors DC operating point, according to the following

(4.6)

(4.7)

 

and r_u is approximated as

(4.8)

 

Also included in the hybrid-model are the ohmic resistances of the three junctions; r_C, r_B (r_x), and r_E.  Note that r_E is not the r_e used in the text by Sedra and Smith.

 

The small-signal parameters of a transistor are usually computed by Spice prior to most analyses.  In many types of analysis, the small-signal model of the BJT is paramount to the analysis.  Spice will list the small-signal model parameters of all transistors in a given circuit when an .OP command is included in the Spice input file.  Because of the importance of the base resistance r_B on small-signal operation, Spice will also list this value amongst the small-signal parameters in the output file. It will be denoted by Rx.

 

As an example of the small-signal parameters that are listed in the Spice output file as a result of an .OP analysis command, we show below the operating point information for transistors Q₁ and Q₂ in our previous example given in subsection 4.3.3:

 

Here we see a list containing the DC operating point and small-signal model parameters for both the npn and pnp transistors in the circuit of Fig. 4.13.  Besides the parameters that have already been explained, this list also contains other parameters, such as capacitances CBE, CBC, CBX and CJS.  These capacitances model dynamic effects of the transistor and will be further explained in Chapter 7. Likewise, BETAAC, and FT, are parameters that are derived from the dynamic small-signal model of the transistor and will also be explained in Chapter 7.

 

 

4.4.2 Single-Stage Voltage-Amplifier Circuits

 

Consider the voltage amplifier circuit shown in Fig.  4.16.  This circuit was presented and analyzed for its voltage gain by Sedra and Smith in Example 4.9 of their text.  Here we shall use Spice to calculate the voltage gain of this circuit assuming that the transistor has a B_F = 100 and I_S=1.8104 x 10^-15 A.  The other parameters of the BJT model will take on their default values.

 

 

In Fig.  4.17 we list the Spice input file for this circuit.  A transfer function command (.TF) is included to calculate the voltage gain v_o/v_i where v_o is taken at node 2.  In addition, we are also requesting an operating point calculation (.OP) so that we may cross-check the results found using the .TF command with those computed by hand using the equations derived by Sedra and Smith, 3^rd Edition, in Example 4.9 of their text.

 

The results of the .TF command are as follows:

 

 

Hence, the voltage gain of this circuit is -2.966 V/V.  Also, the input and output resistance of this circuit are 101.1 k-ohm and 3 k-ohm, respectively.  Referring back to the circuit shown in Fig. 4.16, these resistance levels seem to be in line with what one would expect.  

 

We can collaborate the voltage gain calculation found using the .TF command by performing the same gain calculation using the small-signal equivalent circuit representation of the amplifier circuit shown in Fig.  4.16.  This was performed by Sedra and Smith, and they found that the voltage gain, in terms of the small-signal parameters of the transistor, is given by

(4.9)

 

In this derivation the output resistance of the transistor was assumed infinite.  The small-signal parameters of the hybrid-pi model for this particular transistor as calculated by Spice are found amongst the transistor operating point information in the Spice output file.  A partial listing of the operating point information found in the output file for transistor Q₁ is given below:

 

From the above list, we see that g_m=88.2 mA/V and r_p=1.13 k-ohm.  Substituting these values, together with R_C=3 k-ohm and R_BB=100 k-ohm, into Eqn.  (4.9), one finds the voltage gain to be -2.96 V/V.  Comparing this result with that computed using the .TF command of Spice, as expected, one finds almost exact agreement.  The difference is due the number of significant digits used in the two calculations.  In principle, these two calculations should be in perfect agreement because the .TF command calculates the voltage gain in the exact same way.

 

 

 

Fig. 4.19: The output voltage waveform of the amplifier shown in Fig. 4.16 for two different inputs levels of 0.8 V and 1.1 V. The larger output signal is seen to be clipped on its lower peaks.

 

To visualize the operation of this amplifier, consider simulating the circuit shown in Fig.  4.16 with a time-varying input.  More specifically, we shall consider that v_i is time-varying with a triangular waveform.  We shall consider that the input signal has a period of 1 ms and an input amplitude of 1.1 V.  Moreover, we shall repeat the same example with the input amplitude reduced to 0.8 V.  We shall then want to compare the results.

 

To emulate a triangular waveform, we make use of the following PULSE statement:

 

Vi 4 5 PULSE (-1.1V 1.1V 0 0.5ms 0.5ms 1us 1ms)

 

The rise and fall times are set to equal half the period of the triangle waveform of 1 ms.  Mathematically, the pulse width field should be zero, however, due to a Spice technicality, the pulse width cannot be specified as being equal to zero.  To circumvent this problem, we set the pulse width to a small, but, nonzero value - in this case 1 us.  Furthermore, we added a .TRAN statement to calculate the time response of the circuit over a 4 ms interval.  The resulting Spice input file for the first example is listed in Fig.  4.18.  The same file can be used for the second case by simply reducing the peak level of the input signal from 1.1 V to 0.8 V.  For comparison purposes, we shall concatenate the two files together before submitting the job to Spice.

 

The voltage waveforms at the collector of the amplifier for both input levels, as calculated by Spice, are displayed in Fig.  4.19.  Both signals are riding on a DC component of 3.2 V, corresponding to the DC bias point at the collector.  One will also notice that the larger output waveform is clipped on its lower peak.  This can be traced back to the transistor being forced into its cutoff region when the input signal level exceeds a 0.82 V level.  The other waveform does not appear to be clipped, confirming that the transistor stays out of its cutoff region.

 

Another Example:

 

As another example of a transistor being used to form a linear amplifier, consider the circuit shown in Fig.  4.20.  In this particular case, a pnp transistor is the central component of the design.  This circuit was analyzed by hand by Sedra and Smith, 3^rd Edition, in Example 4.11 of their text.  From their analysis they found that the amplifier had a noninverting voltage gain of 183.3 V/V.  They reasoned that, because the input signal appears directly across the base-emitter junction of the pnp transistor, the input signal amplitude must remain below 10 mV to justify small-signal operation and obtain this voltage gain.  In the following we shall simulate the amplifier circuit shown in Fig. 4.20 subject to a triangular waveform input signal having a peak value of 10 mV and compare it to one with twice the amplitude.

 

The Spice input file for the pnp transistor amplifier circuit shown in Fig.  4.20 subject to a 10-mV triangular input signal is listed below in Fig.  4.21.  The infinite-valued capacitors, C₁ and C₂, are represented in the Spice input file by large 100 uF capacitors that are initially charged to the DC bias voltage that will eventually appear across them.  These are usually found by first determining the DC operating point of the circuit using an .OP command with the input set to zero.  This ``trick'' speeds up the circuit simulation by starting the circuit off near its steady-state operation.  If these initial conditions were not specified, then our transient simulation time would be excessively long.  This stems from the fact that these large coupling capacitors form large time-constants and need a long time to charge to their steady-state values.  Even then, we are still required to allot some simulation time for the circuit to reach its true steady-state operation. This is the reason for delaying the output on the .TRAN statement until 10 ms (or 10 periods of the input signal) after its start.  Also note that we must specify on the .TRAN statement that we want Spice to use the initial conditions established for each capacitor by specifying the field flag UIC.  

 

Submitting this file, concatenated together with another file having a triangular input signal of 20 mV amplitude, to Spice results in the input and output waveforms shown in Fig.  4.22.  The larger output signal in the lower trace due to the 20-mV input signal clearly deviates from an ideal triangle waveform; it looks more parabolic than linear.  The smaller output signal caused by the 10-mV input signal though much more linear, exhibits some deviation from the ideal, thus suggesting that the small-signal linear range of operation is actually less than 10 mV.

 

We also see from Fig. 4.22 that for the 10-mV peak input signal, the corresponding output signal has a peak to peak excursion of 3.5 V, corresponding to a signal gain of 175 V/V. This result is, therefore, in good agreement with the small-signal gain that was calculated by hand (183.3 V/V) in Example 4.11 of Sedra and Smith, 3^rd Edition.

 

 

 

 

 

 

 

Fig. 4.22: Input and output waveforms of the pnp amplifier shown in Fig. 4.20. The top graph displays the two input triangular waveforms and the bottom graph displays the output response to the two input signals. Distortion is evident in both output waveforms.

 

 

4.5 DC Bias Sensitivity Analysis

 

Sensitivity to Component Variations

 

Bias networks are used in transistor amplifier design to establish the proper DC operating point of each transistor.  In order to maintain consistent operation, the DC operating point of each transistor must be held constant. This is normally achieved by a bias network that maintains the emitter current of each transistor relatively constant under potential circuit variations, e.g., variations in transistor B, etc.

 

Provisions have been made in Spice for investigating the DC stability of circuit behavior in the face of component variations through a DC sensitivity analysis.  When invoked, through a .SENS analysis command placed in the Spice input file, Spice will compute the derivatives, or what is also known as the sensitivities, of selected variables of the circuit to most of the components of the circuit.  This includes the sensitivities to many of the model parameters of the BJT, such as B and I_S. If diodes are present in the circuit, the sensitivities to the diode model parameters will also be computed and listed. Unfortunately, Spice does not compute the sensitivities to the FET model parameters.

 

Table 4.3: General form of the DC sensitivity analysis request.

 

 

The general description of the syntax of the Sensitivity Analysis command (.SENS) is provided in Table 4.3.  The command line begins with the keyword .SENS followed by a list of the variables whose derivatives will be computed with respect to the different components of the circuit. The results of the. SENS command are sent directly to the Spice output file in much the same way as that performed by the operating point or transfer function analysis commands seen previously.  No .PRINT or .PLOT statement is required in the Spice input file. It should be noted that Spice first computes the DC operating point of the circuit and then computes the appropriate derivatives.  This next example will demonstrate the results of a Spice sensitivity analysis. 

 

 

Consider the BJT amplifier shown in Fig. 4.23(a) which is biased using a single power supply resistive network arrangement. Let us compute the sensitivities of the emitter current of Q₁ using Spice assuming that the BJT is modeled after the widely available commercial transistor 2N2222A. This requires that we place a zero-valued voltage source V_emitter in the emitter branch of the amplifier circuit to monitor the emitter current, as is shown in Fig. 4.23(b).  The model parameters for the 2N2222A were derived from the information contained on the manufacturer's data sheets for the 2N2222A.  The details of converting manufacturer's data on supplied transistor parts to a Spice model is beyond the scope of this text.  We note, however, that, software is now available from various development houses that greatly simplify this task, e.g., MicroSim Corporation, the suppliers of PSpice. An interesting paper [Malik,1990] describes a step-by-step procedure for determining numerical parameter values for the Spice model of a BJT from manufacturer's measured data.

 

The Spice input file describing this circuit is provided in Fig. 4.24. Here the sensitivity analysis command,

 

.SENS I(Vemitter)

 

will request that Spice compute the sensitivity of the emitter current to various components in the circuit. The results of this analysis are then found in the output file, together with some of the DC bias solution, as follows:

 

 

The above list of sensitivities consists of two parts: the top portion of the table lists the sensitivities to the DC sources and passive components of the circuit and the bottom part of the table lists the sensitivities to the parameters of the models of the active components in the circuit. In this particular case, there is only one active component in the circuit, Q₁. 

 

In the above table, the first column indicates the element that the sensitivity of the emitter current I_E is taken with respect to. The second column indicates the nominal value of that element as it appears in the Spice input file. The third column indicates the sensitivity quantity where x is the corresponding element appearing in the leftmost column. In general, the units of this sensitivity quantity are the units of the output variable specified on the .SENS statement divided by the units of the element x. For instance, in the case of the 3.3 k-ohm emitter resistor R_E, denoted by Re in the above sensitivity list as the fourth element from the top, the sensitivity quantity ¶I_E/¶R_E is expressed in A/ohm and has a value of -2.771 x 10^-7 A/ohm. The final column that appears on the right, is a normalized sensitivity measure. It simply expresses the sensitivity in more convenient units of A/%. Mathematically, it is written as  where is the relative change of R_E expressed in per-cent. For R_E, the normalized sensitivity measure is -9.144 x 10^-6 A/%.

 

From the above sensitivity analysis, we can obtain estimates of how stable the emitter current I_E is in the face of component variations. For example, if the emitter resistor R_E changes by 10% we can expect that the emitter current will approximately change according to the relation

(4.10)

Thus, substituting the appropriate numerical values, we find that a 10% change in R_E results in a 91.4 uA change in the emitter current of Q₁.  This is about 9.5% of its quiescent value of 967.0 uA.

 

Similarly, we can estimate the effect a 20% variation in transistor B_F has on the emitter current of Q₁. Consider from the above Spice generated sensitivities we see that  A/%. Thus, a 20% change in B_F gives rise to a 5.39 uA change in the emitter current of Q₁.  This is about 0.56% of the quiescent value.

 

It should be obvious that this same approach can be used for any of the components of the circuit in Fig. 4.23 whose sensitivities are given in the above table. One can also investigate the effect that different component changes has on the emitter current by making use of the mathematical concept of a total derivative. An example of this is provide in section 5.6 as it applies to a MOSFET amplifier circuit.

 

 

Sensitivity to Temperature Variations

 

To investigate the bias stability of an amplifier subject to temperature changes requires a different approach than that just seen using the sensitivity analysis (.SENS) command of Spice. For such cases, we make use of an extension to the DC sweep command which will allow the user to sweep the temperature of the circuit over a specified range while repeatedly performing a DC analysis.  The syntax of this command is identical to any other DC sweep command with the keyword TEMP replacing the field marked by source_name. The range of temperature values is specified in exactly the same way as for a voltage or current source.  For this particular example, we will monitor the emitter current over a temperature range beginning at 0°C and ending at 125°C in steps of 25°C.  The exact syntax of this DC sweep command can be seen in the Spice input file for this example in Fig. 4.25.

 

 

Fig. 4.26: Temperature variation of the emitter current in the amplifier circuit shown in Fig. 4.23(a).

 

The built-in model for the BJT accounts for variations in temperature.  The same cannot be said for the resistors.  In order to account for changes in resistance due to temperature variations, one must indicate on each resistor statement in the Spice input file its temperature dependence using the two temperature coefficients TC₁ and TC₂.  The formula used by Spice to calculate the value of a resistor at a temperature (Temp) other than 27°C, is given by

(4.11)

 

For our purposes here, we shall consider only the linear dependence of resistance on temperature, and therefore, consider TC₂=0.  We shall assume for this example, that TC₁ = 1200 ppm/°C, where ppm denotes parts-per-million or a multiplication factor of 10^-6.  To specify the dependence of a resistor on temperature in the Spice input file, one simply appends to the resistor statement, after the field indicating the nominal value of the resistor, TC=TC₁.  In this particular case, we will write TC=1200u.  This is also indicated in the Spice input file listed in Fig. 4.25.

 

The results of the emitter current dependence on temperature are summarized in Fig.  4.26. For a 125°C change in circuit temperature, the emitter current changed by no more than 50 uA.  This is sometimes expressed as a temperature coefficient in units of ppm/°C as the ratio of the change in emitter current divided by the emitter current at the nominal temperature of 27°C to the change in circuit temperature creating this current change.  In this case, the emitter bias current has a temperature coefficient of -413 ppm/°C.

 

 

Fig. 4.27: Basic single-stage BJT amplifier configurations: (a) common-emitter amplifier, (b) common-base amplifier and (c) common-collector amplifier.

 

4.6 Basic Single-Stage BJT Amplifier Configurations

 

In this section we shall investigate the three basic types of amplifier configurations shown in Fig. 4.27: the common-emitter (CE), common-base (CB) and common-collector (CC). The primary goal of this section is to determine the small-signal parameters of these amplifiers, such as input resistance R_i, output resistance R_o, voltage gain A_v and current gain A_i, using the AC analysis facility of Spice. These results will then be compared to those predicted by the formulae derived by hand in Sedra and Smith using small-signal analysis. The transistor used in each amplifier of Fig. 4.27 will be assumed modeled after the commercial 2N2222A npn transistor.

 

 

Fig. 4.28: Circuit setups used to determine the amplifier's small-signal parameters: (a) circuit arrangement for computing i_i, v_o and i_o (b) circuit arrangement for computing i_o due to voltage source connected to output terminal of amplifier.

 

 

The Common-Emitter Amplifier

 

As the first example of this section, let us compute the small-signal parameters of the common-emitter (CE) amplifier shown in Fig. 4.27(a).  To obtain all four parameters, i.e., A_v, A_i, R_i and R_o, we will have to run two separate Spice analyses; one for computing the input current and the output voltage for a known voltage applied to the input of the amplifier, and the other for computing the current supplied by a voltage source connected to the output terminal of the amplifier when the input voltage source is set to zero. These two situations are depicted in Fig. 4.28.  In order to monitor the current flowing through the load resistor we placed a zero-valued voltage source in series with it, as shown in Fig. 4.28(a).  The input current to the amplifier can be determine by monitoring the current supplied by the input voltage source v_s.  The four parameters of the amplifier can then be computed from these results according to the following:

(4.12)

(4.13)

(4.14)

(4.15)

 

For the first case depicted in Fig. 4.28(a), consider applying a 10 mV AC signal to the input of the amplifier. A DC input voltage signal would not be useful here since the input source to the amplifier is AC-coupled. Thus, the frequency of the input signal should be selected to be in the midband frequency range of the amplifier. With the choice of decoupling and by-pass capacitors selected here (each selected very large at 1 GF)[1], an input frequency of 1 kHz is sufficiently midband. The Spice input file describing this circuit setup is provided in Fig. 4.29. Both a DC and an AC analysis requests are specified.  The results of the AC analysis will be used to indirectly calculate the small-signal parameters of the amplifier, as mentioned above.  The results of the DC analysis will provide us with the small-signal parameters of the transistor from which we can use the formulae derived in Sedra and Smith to predict the small-signal parameters of the amplifier and compare them to those computed by the indirect AC analysis approach.

 

 

Submitting the Spice input file for processing, we find on completion that the magnitude and phase of the input and output voltage of the amplifier is as follows:

 

 

Thus, we find that this amplifier has a midband voltage gain A_v of -50.68 V/V. Likewise, the input and output currents associated with this amplifier are found to be:

 

 

These two current results indicate that the midband current gain A_i of this amplifier is -74.49 A/A. Finally, the input resistance of the CE amplifier can be computed from the following results,

 

 

Thus, the midband input resistance R_i of this amplifier is 4.7 k-ohm.

 

Repeating this same process but with the input voltage source level set to 0 V and the level of the voltage source in series with the load resistance increased to 10 mV AC, we can determine the output resistance of this amplifier.  This requires that we modify the statements for these two AC sources in the Spice deck seen listed in Fig. 4.29 to read as follows:

 

Vs   6 0 AC 0V

Vout 9 0 AC 10mV

          

Further, to access the resulting current supplied by the output voltage source V_out and the voltage developed across the output terminal of the CE amplifier, we include the following PRINT statement in the Spice deck:

 

.PRINT AC Vm(7) Vp(7) Im(Vout) Ip(Vout)

 

Re-running the Spice job, we find the following results in the output file:

 

 

From these results we compute the output resistance R_o to be 8.97 k-ohm.

 

To compare the above results with those predicted by hand analysis, we list below the expressions for A_v, A_i, R_i and R_o in terms of the small-signal model parameters of the transistor, as derived in section 4.11 of Sedra and Smith:

(4.16)

(4.17)

 

(4.18)

 

 

(4.19)

 

Here B is the small-signal transistor current gain[2] defined in terms of g_m and r_p according to:

(4.20)

 

 

With the inclusion of the .DC operating point command in the above mentioned Spice decks we find that the parameters of the hybrid-pi model for the 2N2222A transistor of the common-emitter amplifier are as follows:

Substituting the appropriate parameter value, together with values for the different circuit components, we find:  A_v=-52.3 V/V, A_i=-78.0 A/A, R_i=4.69 k-ohm and R_o=8.97 k-ohm. To compare these with those computed indirectly by Spice above, we list in Table 4.4 a comparison of the results of these two approaches.  The first and second column of this table list the small-signal parameters of the amplifier and its formula in terms of the small-signal transistor model parameters. The third and fourth columns indicate the value predicted by hand analysis and that obtained indirectly with Spice. The fifth column indicates the relative difference between the two results as a means of indicating how accurate the hand analysis is.  As is evident from the results listed in this table, the results compare quite well.

 

 

 

Table 4.4: Comparing the small-signal amplifier parameters of the common-emitter amplifier shown in Fig. 4.27(a) as calculated by hand analysis and that indirectly computed using Spice.

 

 

To demonstrate the usefulness of small-signal analysis, let us apply a small-amplitude sinusoidal signal to the input of the amplifier and observe the time-varying signal that appears at the output of this amplifier.  Say for the sake of illustration, we apply a 10-mV sinusoidal of 1 kHz frequency to the input of the amplifier. The Spice deck for this particular situation is provided in Fig. 4.30. A transient analysis command is specified to compute the output waveform over three cycles of the input signal beginning at a time of 5 ms. This is to ensure that the circuit has had sufficient time to reach steady state. The dc-coupling and bypass capacitors have been assigned more practical values of 10 uF each, unlike those used in the previous AC analysis. In this way, the time to reach steady state is drastically reduced. One should note that by the very nature of a Spice transient analysis, the analysis performed here is a large-signal analysis and not a small-signal analysis even though the input signal level is small.

 

The results of the transient analysis are shown in Fig. 4.31. The top graph displays the 10-mV peak, 1 kHz input sinusoidal signal and the bottom graph displays the corresponding output signal. With the aid of Probe, we found that the amplitude of the output signal is 500 mV. Thus, the voltage gain of this amplifier is seen to be about -50 V/V, which agrees with that predicted by the two analyses above.

 

 

 

Fig. 4.31: The input and output time-varying voltage waveforms associated with the common-emitter amplifier shown in Fig. 4.27(a).

 

 

The Common-Base Amplifier

 

Another important amplifier configuration is the common-base (CB) amplifier shown in Fig. 4.27(b). Here the base of the transistor is AC grounded, the input signal source is connected to the emitter, and the load is connected to the collector. In the following we shall repeat the analysis method carried out on the common-emitter amplifier using Spice and compare the results with those estimated by the small-signal formulas derived by hand analysis.

 

The Spice input file for this common-base amplifier is shown in Fig. 4.32. Like the previous case of the common-emitter amplifier, a zero-valued voltage source is placed in series with the 10 k-ohm load resistor. This voltage source is used to monitor the current supplied to the load resistor. It will also be used to determine the output resistance of the amplifier. Both a DC and an AC analysis are specified. The DC analysis will provide us with the small-signal model parameters of the transistor. The AC analysis will enable us to determine the current supplied to the amplifier by the input voltage source, and the voltage and current supplied to the load resistor.

 

 

Submitting the Spice input file for processing, we find on completion that the magnitude and phase of the input and output voltage of the amplifier are as follows:

 

 

Therefore, we determine that this common-base amplifier has a midband voltage gain A_v of +60.96 V/V. Likewise, the input and output current associated with this amplifier are found to be:

 

 

Thus, the input current to the amplifier is 123.1 uA and the current supplied to the load is 60.96 uA, giving a current gain 0.495 A/A. Finally, the input resistance of the CB amplifier can be computed from the following results,

 

 

Thus, the midband input resistance R_i is 31.2 ohm.

 

Repeating this same process but with the input voltage source level set to 0 V and the level of the voltage source in series with the load resistance increased to 10 mV AC, we find that the output resistance R_o of this amplifier is 9.58 k-ohm. This was found from another Spice run of a modified version of the Spice deck shown in Fig. 4.32 where the two AC input and output voltage sources were modified to read as follows:

 

Vs   6 0 AC 0V

Vout 9 0 AC 10mV

          

and the following PRINT statement was added to the Spice deck:

 

.PRINT AC Vm(7) Vp(7) Im(Vout) Ip(Vout)

 

The results of this analysis are then found below:

 

 

As a means of comparison, we summarize in Table 4.5 the small-signal formulae pertinent to the common-base amplifier derived by hand in Sedra and Smith, together with their values as calculated by substituting the relevant transistor small-signal model parameters into each equation. The small-signal model parameters for the 2N2222A transistor are identical to those found in the common-emitter case in the previous subsection.  This is not too surprising given that the transistor of the common-base amplifier is biased in exactly the same manner as in the common-emitter amplifier. This was also confirmed by the DC analysis performed by Spice on the common-base amplifier. A fourth column is also included in this table listing the small-signal parameters computed from the Spice analysis above.  As is evident from the fifth column, indicating the relative error between the two methods of estimating the amplifier small-signal parameters, we see that they are in good agreement.

 

 

 

Table 4.5: Comparing the small-signal parameters of the common-base amplifier shown in Fig. 4.27(b) as calculated by hand analysis to those indirectly computed using Spice.

 

 

 

Table 4.6: Comparing the small-signal parameters of the common-collector amplifier shown in Fig. 4.27(c) as calculated by hand analysis to those indirectly computed using Spice.

 

 

The Common-Collector Amplifier

 

This same analysis can be repeated for the common-collector (CC) amplifier configuration shown in Fig. 4.27(c). Rather than list much of the same as that seen previously, we simply summarize the results in Table 4.6. As before, the Spice results are in good agreement with those obtained with hand analysis.

 

4.7 The Transistor as a Switch

 

As the final example of this chapter, consider the simple transistor switching circuit shown in Fig.  4.33.  This particular circuit was designed by Sedra and Smith in Example 4.14 of their text such that transistor Q₁ is in saturation with an overdrive factor larger than 10 when the transistor has a minimum B of 50.  With the aid of Spice, we would like to determine the overdrive factor of the transistor in this circuit when the transistor is assumed to be the commercial 2N696 npn device and the base driving voltage V_BB equals 5 V.

 

The overdrive factor (OD) of a saturated transistor is defined as the ratio of the base current I_B divided by the minimum base current that will force the transistor into saturation, denoted as I_Bsat. Thus,

(4.21)

 

Correspondingly, at the minimum base current condition, the transistor is beginning to conduct a collector current I_Csat. Moreover, as the device is driven further into saturation the collector current remains fairly constant at I_Csat. Thus, the point at which the collector current begins to saturate denotes the edge of the saturation region. Using Spice, we shall compute the input condition that gives rise to the transistor entering its saturation region in the circuit of Fig. 4.33. This can be accomplished by sweeping the base driving voltage V_BB between ground and 5 volts and observing both the collector current and the base current of the transistor.  From this, we can then determine the base current I_Bsat. Moreover, at V_BB=5 V, we can determine the base current I_B and thus the overdrive factor OD for this particular circuit.

 

Fig. 4.35: The collector and base current characteristics of the transistor in the circuit of Fig. 4.34 as functions of the base driving voltage V_BB. The top curve displays the collector current and the bottom trace displays the base current.

 

 

The Spice input file for the switching circuit shown in Fig. 4.33 is listed in Fig. 4.34.  A DC sweep analysis is requested that varies the input voltage V_BB between 0 and 5 volts in 0.1-volt increments. The BJT model parameters for the 2N696 npn transistor are also listed. These were derived from nominal device characteristics.

 

The results of the Spice analysis are shown plotted in Fig. 4.35. The upper trace displays the transistor collector current I_C as a function of the base driving voltage V_BB, and the lower trace displays the corresponding base current for the same input voltage. Using the cursor feature in Probe we find from the plot of collector current that the collector current begins to saturate at a current level of 9.79 mA when the base driving voltage V_BB exceeds 1.4 V.  Correspondingly, from the trace of the transistor base current, we find that at an input voltage V_BB of 1.4 V, the base current is 313.6 uA. Hence, I_Bsat=313.6 uA. Also, we find at an input voltage level of V_BB=5 V, the transistor base current I_B is 1.932 mA.  Therefore, using Eqn. (4.21), we compute the overdrive factor OD for transistor Q₁ to be 6.16.

 

4.8 Spice Tips

 

·      A BJT is described to Spice using an element statement and a model statement. 

 

·      The element statement describes how the base, collector, and emitter of a transistor are connected to the rest of the network. 

 

·      The model statement contains a list of parameters describing the terminal characteristics of a BJT using the built-in model of Spice. 

 

·      There are 40 parameters associated with the built-in Spice model of the BJT. (We discussed only 6 of them, the remainder are described in the Appendix). 

 

·      A specific transistor mode of operation is deduced from the DC voltages that appears across its emitter-base junction and collector-base junction. This information can be found in the Spice output file as a result of an operating point (.OP) analysis.

 

·      When an operating point (.OP) calculation is included in the Spice input file, a list of operating point information for each transistor is obtained. This information contains DC bias conditions for the transistor and the parameters associated with its small-signal model.

 

·      Models of many commercial bipolar transistors are available from various semiconductor manufacturers. A library of transistor models for various commercial transistors are available with the PSpice program.

 

·      Spice can be used to generate families of {\it i-v} curves for transistors, just like the laboratory curve-tracer instrument. 

 

·      A DC sweep command can be extended to include a sweep of temperature, allowing one to investigate the circuits dependence on temperature. 

 

·      The pulse width of a time-varying waveform generated by the PULSE source statement of Spice cannot be made equal to zero.  Instead, a value that is much smaller, at least several orders of magnitude less, than the period of the waveform is assigned to the pulse width.

 

·      The DC sensitivities of a circuit can be computed using the  .SENS analysis command. This command will compute the sensitivities of a particular circuit variable to most of the components in the circuit. This includes the sensitivities of many of the model parameters of the BJT.

 

·      If the effect of decoupling and by-pass capacitors is to be ignored then their values should be selected to be very large during the simulation (generally, a good value is 1 GF).

4.9 Bibliography

 

L. W. Nagel, SPICE2 - A computer program to simulate semiconductor circuits, Memorandum no. ERL-M520, May 1975, Electronic Research Laboratory, University of California, Berkeley.

 

N. R. Malik, Determining Spice parameter values for BJT's, IEEE Transaction on Education, vol. 33, No. 4, pp. 366-368, Nov. 1990.

 

4.10 Problems

 

4.1.         Consider the case of a transistor whose base is connected to ground, the collector is connected to a 10 V dc source through a 1 k-ohm resistor, and a 5-mA current source is connected to the emitter with the polarity so that current is drawn out of the emitter terminal. If B_F=100 and I_S =10^-14 A, find the voltages at the emitter and the collector using Spice. Further, determine the base current. 

 

4.2.         Using the Spice model parameters for the commercial 2N2222A npn BJT given in Section 4.5, determine its leakage current I_CBO at room temperature (i.e., 27°C). If the temperature of the device is raised to 75°C, what is the new I_CBO? {\it Hint: Connect the base to ground, the collector to +5 V, and do not connect the emitter terminal.  The current supplied by the +5 V voltage source is I_CBO.

 

4.3.         Consider a pnp transistor having I_S=10^-13 A and B_F=40. If the emitter is connected to ground, the base is connected to a current source that pulls out of the base terminal a current of 10 uA, and the collector is connected to a negative supply of -10 V via a 10 k-ohm resistor, find the base voltage, the collector voltage, and the emitter current using the operating point (.OP) command of Spice.

 

4.4.         Using Spice as a curve tracer, plot the i_C - v_CE characteristics of an npn transistor having I_S=10^-15 A and V_A=100 V. Provide curves for v_BE=0.65, 0.70, 0.72, 0.73 and 0.74 volts. Show the characteristics for v_CE up to 15 V.}

 

4.5.         For a BJT having an Early voltage of 200 V, what is its output resistance at 1 mA as calculated by Spice? at 100 uA?

 

4.6.         The transistor in the circuit of Fig. P4.6 has a very high B_F (assume at least 10⁶ in the Spice file). The other parameters of the transistor Spice model can assume default values. Find V_E and V_C for V_B equal to (a) +3 V, (b) +1 V, and (c) 0 V. What is the transistor mode of operation in each case?

 

 

         

Fig. P4.6                                                                      Fig. P4.9

 

4.7.         For the circuit in Fig. P4.6, with the aid of Spice and V_B set equal to +2 V, find all node voltages for (a) B_F very high (>10⁶), and (b) B_F=99.

 

4.8.         In the circuit of Fig. 4.16, the input signal v_i is described by 0.004 sin(wt) volts and the transistor is assumed modeled after the 2N2222A type.  In addition, V_BB is reduced from 3 V to 1 V.  Using Spice, plot the base and collector current of Q₁ as a function of time for at least one period of the input signal. Likewise, plot the collector voltage of Q₁. What is the voltage gain of this amplifier?

 

4.9.         The transistor shown in the circuit of Fig. P4.9 has B_F=100 and V_A=80 V. Use Spice to answer the following questions, but also compare your results with those obtained through a hand analysis:

a)      Find the dc voltages at the base, emitter, and collector using Spice.  Represent the infinite-valued capacitors with a very large, but finite, value.

b)      Find g_m, r_p, and r_o.

c)       If terminal Z is connected to ground, X to signal source V_s having a 10 k-ohm source resistance, what is the voltage gain v_y/v_s. Since the capacitor connected to node Y is left floating, either connected a large load to node Y or remove this capacitor and take the measurement directly from the collector of the transistor.

d)      If terminal X is connected to ground, Z to an input signal source v_s having a 200 ohm source resistance, and Y to a load resistance of 10 k-ohm, find the voltage gain v_y / v_s.

e)      If terminal Y is connected to ground, X to an input signal source v_s having a 100 k-ohm source resistance, and Z to a load resistance of 1 k-ohm, find the voltage gain v_z / v_s.

 

4.10.      With the aid of Spice, verify the design of a version of the circuit in Fig. 4.23 that uses ±9.5 V supplies for operation at 10 mA (for high B_F), such that the total variation in I_E is less than 5% for B_F as low as 50.  To obtain the highest possible voltage gain, select the largest possible value for R_C; however, you must ensure that V_CE is never less than 2 V.

 

Fig. P4.11

 

4.11.      For the common-emitter amplifier shown in Fig. P4.11, let V_CC=9 V, R₁=27 k-ohm, R₂=15 k-ohm, R_E=1.2 k-ohm, and R_C=2.2 k-ohm. The transistor has B_F=100 and V_A=100 V. Using Spice, calculate the dc bias current I_E. If the amplifier operates between a source for which R_s=10 k-ohm and a load of 2 k-ohm, determine the values of R_i, G_m, R_o, A_v, and A_i.

 

4.12.      Repeat Problem 4.11 with the transistor modeled after the commercial transistor 2N696. Use the Spice parameters for the 2N696 provided in Section 4.6.

Fig. P4.13

4.13.      The amplifier of Fig. P4.13 consists of two identical common-emitter amplifiers connected in cascade.

a)      For V_CC=15 V, R₁=100 k-ohm, R₂=47 k-ohm, R_E=3.9 k-ohm, R_C=6.8 k-ohm, and B_F=100, determine the dc collector current and collector voltage of each transistor using Spice. The amount of data that must be typed into the computer is reduced if a subcircuit is created for one of the stages and used twice to form the overall amplifier.

b)      Find R_in1 and v_b1/v_s for R_s=5 k-ohm.

c)       Find R_in2 and v_b2/v_b1 for R_s=5 k-ohm.

d)      For R_L=2 k-ohm, find v_o/v_s.

 

Fig. P4.14

4.14.      For the emitter-follower circuit shown in Fig. P4.14 the BJT used is specified to have B_F values in the range of 20 to 200. For the two extreme values of B find:

a)      I_E, V_E and V_B.

b)      the input resistance R_i.

c)       the voltage gain v_o/v_s.

 

Fig. P4.15

 

4.15.      For the bootstrapped follower circuit shown in Fig. P4.15 where the transistor is assumed to be of the 2N2222A type, compare the input and output resistance, and the voltage gain v_o/v_s, with and without the bootstrapping capacitor C_B in place.

 

4.16.      One small-signal BJT model parameter that is used in the small-signal calculations of Spice but is not sent to the Spice output file when an .OP command is specified is r_u. Devise a simple circuit arrangement for calculating this small-signal resistance with Spice.